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| DR8051XP High Performance Configurable 8-bit Microcontroller ver 3.10 OVERVIEW DR8051XP is a high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about low power consumption. Additionally an advanced power management unit makes DR8051XP core perfect for portable equipment where low power consumption is mandatory. DR8051XP soft core is 100% binarycompatible with the industry standard 8051 8bit microcontroller. There are two configurations of DR8051XP: Harward where external data and program buses are separated, and von Neumann with common program and external data bus. DR8051XP has RISC architecture 6.7 times faster compared to standard architecture and executes 65-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked up to seven times more slowly than the original implementation for no performance penalty. DR8051XP is fully customizable, which means it is delivered in the exact configuration to meet users' requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench All trademarks mentioned in this document are trademarks of their respective owners. with complete set of tests allowing easy package validation at each stage of SoC design flow. CPU KEY FEATURES 100% software compatible with industry standard 8051 RISC architecture enables to execute instructions 6.7 times faster compared to standard 8051 12 times faster multiplication 9.6 times faster division 2 Data Pointers (DPTR) for faster memory blocks copying Advanced INC & DEC modes Auto-switch of current DPTR Up to 256 bytes of internal (on-chip) Data Memory Up to 64K bytes of Program Memory Up to 16M bytes of external (off-chip) Data Memory User programmable Program Memory Wait States solution for wide range of memories speed User programmable External Data Memory Wait States solution for wide range of memories speed http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. De-multiplexed Address/Data bus to allow easy connection to memory Interface for additional Special Function Registers Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states Scan test ready 1.3 GHz virtual clock frequency in a 0.35u technological process Up to 8 interrupt sources from peripherals Four 8-bit I/O Ports Bit addressable data direction for each line Read/write of single line and 8-bit group Three 16-bit timer/counters Timers clocked by internal source Auto reload 8/16-bit timers Externally gated event counters Full-duplex serial port Synchronous mode, fixed baud rate 8-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, fixed baud rate 9-bit asynchronous mode, variable baud rate PERIPHERALS DoCDTM debug unit Processor execution control Run Halt Step into instruction Skip instruction Read-write all processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware execution breakpoints Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware breakpoints activated at a certain Program address (PC) Address by any write into memory Address by any read from memory Address by write into memory a required data Address by read from memory a required data Three wire communication interface I2C bus controller - Master 7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation I2C bus controller - Slave NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies User defined data setup time on I2C lines Interrupt generation SPI - Master and Slave Serial Peripheral Interface Supports speeds up 1/4 of system clock Mode fault error Write collision error Four transfer formats supported System errors detection Allows operation from a wide range of system Power Management Unit Power management mode Switchback feature Stop mode clock frequencies (build-in 5-bit timer) Interrupt generation Extended Interrupt Controller 2 priority levels Up to 7 external interrupt sources All trademarks mentioned in this document are trademarks of their respective owners. Programmable Watchdog Timer 16-bit Compare/Capture Unit Events capturing http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring * Memory style * Program Memory type * Program Memory waitstates - Harward - von Neumann - synchronous - asynchronous - used (0-7) - unused - used - unused - synchronous - asynchronous - used (0-7) - unused - used - unused - used - unused - used - unused subroutines location Fixed-Point arithmetic coprocessor Multiplication - 16bit * 16bit Division - 32bit / 16bit Division - 16bit / 16bit Left and right shifting - 1 to 31 bits Normalization * Program Memory writes * Internal Data Memory type * * External Data Memory wait-states Second Data Pointer (DPTR1) Floating-Point arithmetic coprocessor IEEE754 standard single precision FADD, FSUB - addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM - compare FCHS - change sign FABS - absolute value * Data Pointers decrement * Data Pointers auto-switch * Interrupts * Timing access protection * Power Management Mode * Stop mode * DoCD debug unit - used - unused - used - unused - used - unused - used - unused Floating-Point math coprocessor - IEEE-754 standard single precision real, word and short integers FADD, FSUB- addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM- compare FCHS - change sign FABS - absolute value FSIN, FCOS- sine, cosine FTAN, FATAN- tangent, arcs tangent Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file. DELIVERABLES CONFIGURATION The following parameters of the DR8051XP core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet http://www.DigitalCoreDesign.com http://www.dcd.pl All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance SYMBOL clk reset ramdatai(7:0) Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support sfrdatai(7:0) LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist prgdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe prgdatao(7:0) prgdataz prgaddr(15:0) prgrd prgwr xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr xramdatai(7:0) int0 int1 int2 int3 int4 int5 int6 docddatai port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) t0 gate0 t1 gate1 t2 t2ex capture0 capture1 capture2 capture3 rxd0i rxd1i mscli msdai sscli ssdai ss si mi scki docddatao docdclk stop pmm port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0) One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs rxd0o txd0 rxd1o txd1 msclhs msclo msdao ssclo ssdao sso(7:0) so mo scko sckz All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM clk reset prgdatai(7:0) prgdatao(7:0) prgdataz prgaddr(15:0) prgrd prgwr xramdatai(7:0) xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatai(7:0) sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe docddatai docddatao docdclk Opcode Decoder ALU PINS DESCRIPTION PIN clk reset ramdatai[7:0] TYPE input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input output output output output output output output output output DESCRIPTION Global clock Global synchronous reset Data bus from Internal Data Memory Data bus from user SFRs Input data bus from Program Memory Data bus from External Data Memory External interrupt 0 line External interrupt 1 line External interrupt 2 line External interrupt 3 line External interrupt 4 line External interrupt 5 line External interrupt 6 line DoCDTM data input Port 0 input Port 1 input Port 2 input Port 3 input Timer 0 clock line Timer 0 clock line gate control Timer 1 clock line Timer 1 clock line gate control Timer 2 clock line Timer 2 control Timer 2 capture 0 line Timer 2 capture 1 line Timer 2 capture 2 line Timer 2 capture 3 line Serial receiver input 0 Serial receiver input 1 Master I2C clock line input Master I2C data input Slave I2C clock line input Slave I2C data input SPI slave select SPI slave input SPI master input SPI clock input Data bus for Internal Data Memory Internal Data Memory address bus Internal Data Memory output enable Internal Data Memory write enable Data bus for user SFRs User SFRs address bus User SFRs output enable User SFRs write enable Program Memory address bus Program Memory Interface sfrdatai[7:0] Control Unit prgdatai[7:0] xramdatai[7:0] int0 int1 int2 int3 int4 int5 int6 port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0) int0 int1 int2 int3 int4 int5 int6 docddatai port0i[7:0] port1i[7:0] port2i[7:0] port3i[7:0] t0 gate0 t1 gate1 External Memory Interface Interrupt Controller Internal Data Memory Interface I/O Ports User SFR Interface DoCDTM Debug Unit Power Management Unit stop pmm Floating Point Unit Multiply Divide Unit t2 t2ex capture0 t0 gate0 t1 gate1 t2 t2ex capture1 capture2 capture3 rxd0i rxd1i mscli msdai sscli ssdai ss si mi scki ramdatao[7:0] ramaddr[7:0] ramoe ramwe sfrdatao[7:0] sfraddr[7:0] sfroe sfrwe prgaddr[15:0] Timer 2 Timers 0 & 1 capture0 capture1 capture2 capture3 rxd1o rxd1i txd1 msclhs mscli msclo msdai msdao sscli ssclo ssdai ssdao Compare Capture Unit Watchdog Timer UART 1 UART 0 rxd0o rxd0i txd0 so si mo mi scko scki sckz ss sso(7:0) Master I2C Unit SPI Unit Slave I2C Unit All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. prgdatao[7:0] prgdataz prgrd prgwr xramdatao[7:0] xramdataz xramaddr[23:0] xramrd xramwr docddatao docdclk pmm stop port0o[7:0] port1o[7:0] port2o[7:0] port3o[7:0] rxd0o txd0 rxd1o txd1 msclo msclhs msdao msclo msdao sso[7:0] so mo scko sckz output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output Output data bus for Program Memory PRGDATA tri-state buffers control line Program Memory read Program Memory write Data bus for External Data Memory XDATA tri-state buffers control line External Data Memory address bus External Data Memory read External Data Memory write DoCDTM data output DoCDTM clock line Power management mode indicator Stop mode indicator Port 0 output Port 1 output Port 2 output Port 3 output Serial receiver output 0 Serial transmitter line 0 Serial receiver output 1 Serial transmitter line 1 Master I2C clock output High speed Master I2C clock line Master I2C data output Slave I2C clock output Slave I2C data output SPI slave select lines SPI slave output SPI master output SPI clock output SPI clock line tri-state buffer control UNITS SUMMARY ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit, logic unit, multiplier and divider. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. Control Unit - Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks. Program Memory Interface - Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new program into RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCDTM module. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. External Memory Interface - Contains memory access related registers such as Data Pointer High (DPH0, DPH1), Data Pointer Low (DPL0, DPL1), Data Page Pointer (DPP0, DPP1), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. Allows applications software to access up to 16 MB of external data memory. The DPP0, DPP1 registers are used for segments swapping. STRETCH register allows flexible timing management while accessing different speed system devices by programming XRAMWR and XRAMRD pulse width between 1 - 8 clock periods. Internal Data Memory Interface - Internal Data Memory interface controls access into the internal 256 bytes memory. It contains 8-bit Stack Pointer (SP) register and related logic. User SFRs Interface - Special Function Registers interface controls access to the special registers. It contains standard and used defined registers and related logic. User defined external devices can be quickly accessed (read, written, modified) using all direct addressing mode instructions. All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Interrupt Controller - Interrupt control module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers. I/O Ports - Block contains 8051's general purpose I/O ports. Each of port's pin can be read/write as a single bit or as an 8-bit bus called P0, P1, P2, P3. Power Management Unit - Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications. DoCDTM Debug Unit - it's a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other onchip debuggers DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. Floating Point Unit - Block contains floating point arithmetic IEEE-754 compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of All trademarks mentioned in this document are trademarks of their respective owners. sign. Basing on specialized CORDIC algorithm a full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface allows easy usage and interfacing with user C/ASM written programs. Multiply Divide Unit - It's a fixed point fast 16-bit and 32-bit multiplication and division unit. It provides shift and normalize operations, additionally. All operations are performed using unsigned integer numbers. The MDU contains MD0 to MD5 operands, the result registers and one control register called ARCON. This unit has included standard software interface allows easy usage and interfacing with user C/ASM written programs. Timers - System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 CLK periods when appropriate timer is enabled. In the counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs. Timer 2 - Second system timer module contains one 16-bit configurable timer: Timer 2 (TH2, TL2), capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit autoreload timer / counter. It also supports compare capture unit if it's presented in system. It can be used as clock source for UART0. Compare Capture Unit - The compare / capture / reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing such as pulse generation, pulse width modulation, measurements etc. Watchdog Timer - The watchdog timer is a 27-bit counter which is incremented every system clock periods (CLK pin). It performs system protection against software upsets. UART0 - Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2. UART1 - Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF1 loads the transmit register, and reading SBUF1 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer 1. Master I2C Unit - I2C bus controller is a Master module. The core incorporates all features required by I2C specification. Supports both 7bit and 10-bit addressing modes on the I2C bus. It works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization to allow it operate in multi-master systems. Built-in timer allows operation from a wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast and High Speed up to 3400 kbs. Slave I2C Unit - I2C bus controller is a Slave module. The core incorporates all features required by I2C specification. It works as a slave transmitter/receiver depending on working mode determined by a master device. The I2C controller supports all transmission modes: Standard, Fast and High Speed up to 3400 kbs. SPI Unit - it's a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling All trademarks mentioned in this document are trademarks of their respective owners. of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. SPI automatically drives slave select outputs SSO[7:0], and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiplemaster mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. PERFORMANCE The following tables give a survey about the Core area and performance in ASICs Devices (all key features have been included): Device 0.25u typical 0.25u typical Optimization area speed Fmax 100 MHz 200 MHz 40000 35000 30000 25000 20000 15000 10000 5000 0 80C51 (12MHz) DR8051XP (200MHz) 268 1550 36996 Core performance in ASIC devices For a user the most important is application speed improvement. The most commonly used arithmetic functions and their improvements are shown in table below. An improvement was computed as {80C51 clock periods} divided by {DR8051XP clock periods} required to execute an identical function. More details are available in core documentation. Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement: Improvement 7,20 6,00 6,00 7,20 7,20 6,00 6,00 7,20 10,67 9,60 7,20 7,64 9,75 7,20 7,43 9,04 7,58 80C310 (33MHz) Area utilized by the each unit of DR8051XP core in vendor specific technologies is summarized in table below. Component CPU* DPTR1 register DPTR0 decrement DPTR1 decrement DPTR0 & DPTR1 auto-switch Timed Access protection Area [Gates] [FFs] 4900 300 100 100 50 100 220 32 8 10 Interrupt Controller INT2-INT6 500 350 40 25 Dhrystone Benchmark Version 2.1 was used to measure Core performance. The following table gives a survey about the DR8051XP performance in terms of Dhrystone/sec and VAX MIPS rating. Device 80C51 80C310 DR8051XP Target 0.25u Clock Dhry/sec frequency (VAX MIPS) 12 MHz 268 (0.153) 33 MHz 1550 (0.882) 200 MHz 36996 (21.000) Power Management Unit I/O ports Timers Timer 2 UART0 UART1 Master I2C Unit Slave I2C Unit SPI Unit Compare Capture Unit Watchdog Timer Multiply Divide Unit Total area 50 400 600 600 700 700 900 550 450 550 400 1700 14000 5 35 50 60 60 60 120 70 55 60 45 105 1060 *CPU - consisted of ALU, Opcode Decoder, Control Unit, Program & Internal & External Memory Interfaces, User SFRs Interface Core components area utilization Core performance in terms of Dhrystones All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. The main features of each DR8051XP family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Program Memory Wait States Architecture speed grade Compare/Capture Interrupt sources Stack space size Timer/Counters Interrupt levels Master I2C Bus Controller Slave I2C Bus Controller Design DR8051CPU DR8051 DR8051XP 6.7 64k 256 256 16M 6.7 64k 256 256 16M 6.7 64k 256 256 16M 2 5 15 2 2 2 1 1 2 2 3 1 2 4 4 - - - - - - DR8051 family of High Performance Microcontroller Cores The main features of each DR80390 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Program Memory Wait States Architecture speed grade Compare/Capture Interrupt sources Stack space size Timer/Counters Interrupt levels Master I C Bus Controller Slave I2C Bus Controller Design DR80390CPU 6.7 16M 256 256 16M DR80390 6.7 16M 256 256 16M DR80390XP 6.7 16M 256 256 16M 2 5 15 2 2 2 1 1 2 2 3 1 2 4 4 - - - - - - DR80390 family of High Performance Microcontroller Cores All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Fixed Point Coprocessor Floating Point Coprocessor - Data Pointers Watchdog I\O Ports UART 2 SPI Fixed Point Coprocessor Floating Point Coprocessor - Data Pointers Watchdog I\O Ports UART SPI CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: iinffo@dcd..pll n o@dc d p tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245, USA e-mail: iinffoUS@dcd..pll n oUS@dcd p tel. fax : +1 210 422 8268 : +1 210 679 7511 Distributors: Please check htttp::///www..dcd..pll//aparrttn..php h p www dcd p apa n php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. |
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